Programmable logic devices (PLDs) have been constantly evolving to include a greater number of logic gates along with additional memory to support various memory intensive applications. The memory is often arranged as blocks of memory (one example of which is referred to as embedded memory blocks (EMBs)), with the blocks typically aligned in rows and/or columns. The memory may be formed, for example, from static random access memory (SRAM) cells, which may be configured to function in various modes (e.g., first-in-first out (FIFO), RAM, or read only memory (ROM)) having different data/address bus widths.
After a PLD is powered-up and configured and depending upon the intended application, the contents of the memory may be unknown (e.g., a do not care condition when used as RAM). Alternatively, it may be desired that the contents of one or more of the blocks of memory be known or pre-defined (e.g., when used as ROM) as the PLD begins to perform its user-defined functions (i.e., user mode or normal mode). If the contents of the memory must be known (pre-defined), the blocks of memory generally must be initialized (pre-loaded) with the desired information (e.g., configuration data via a configuration bitstream) during configuration of the PLD.
For example, one technique for initializing the memory is to view a row (or column) of the blocks of memory as one large memory block and access the address and data lines of the blocks of memory in that row (column) at the same time to write a very wide word into one address of the large memory block. One drawback of this technique is that if only one block of memory requires initialization, the whole row (or column) of the blocks of memory has to be initialized and the equivalent amount of configuration data for all of the blocks of memory in that whole row has to be downloaded. This may add considerably to the time required to configure the PLD and also waste bitstream storage space.
As another example, a system bus may be embedded into a PLD (e.g., a complex programmable logic device (CPLD), a field programmable gate array (FPGA), or a programmable interconnect device) to access the blocks of memory in RAM mode, each with its own bus address. Thus, each block of memory can be independently initialized via the system bus as the bitstream data is transferred by following a bus protocol. Further details regarding an exemplary system bus may be found in U.S. Pat. No. 6,483,342, which is incorporated herein by reference in its entirety.
One drawback of the conventional embedded system bus technique is that as the number of blocks of memory increases, it becomes difficult to extend the system bus to all of the blocks of memory distributed within the PLD without encountering possibly unacceptable system bus performance. Furthermore, if more than one block of memory needs to be initialized with the same data, then the same bitstream content must be repeatedly downloaded through the system bus because each block of memory has its own unique address. Thus, for memory initialization, this conventional system bus technique may add considerably to the time required to configure the PLD and waste bitstream storage space. As a result, there is a need for improved techniques for initializing memory within a programmable logic device.